000 01231nam a2200433 4500
001 vtls000090561
003 VRT
005 20240802185508.0
008 1012070116s2003 maua 001 0 eng ,
010 _a2003-041995
020 _a1402074018
035 _aVNU070101278
039 9 _a201808060946
_bhaianh
_c201502080844
_dVLOAD
_y201012071129
_zVLOAD
041 _avie
042 _apcc
044 _aVN
050 0 0 _aTK7885.7
_b.B47 2003
082 0 0 _a621.381 5
_bBER 2003
_221
090 _a621.381 5
_bBER 2003
100 1 _aBergeron, Janick.
245 1 0 _aWriting testbenches :
_bfunctional verification of HDL models /
_cby Janick Bergeron.
250 _a2nd ed.
260 _aBoston :
_bKluwer Academic Publishers,
_c[2003].
300 _axxix, 475 p. :
_bill. ;
_c25 cm.
650 0 _aComputer hardware description languages.
650 0 _aIntegrated circuits
_xVerification.
650 0 _aMechatronics Engineering Technology
650 0 _aElectronics.
650 0 _aKỹ thuật
650 0 _aTích hợp
650 0 _aĐiện tử
900 _aTrue
911 _aTrần Thị Thanh Nga
912 _aHoàng Thị Hòa
925 _aG
926 _a0
927 _aSH
942 _c1
999 _c370024
_d370024